FPGA Implementation of Data Flow Graphs for Digital Signal Processing Applications

Authors

  • Hala AL-Zu'bi Jordan University of Science and Technology
  • Osama Al-Khaleel Jordan University of Science and Technology
  • Ali Shatnawi Jordan University of Science and Technology

DOI:

https://doi.org/10.17762/ijcnis.v13i1.4928

Abstract

A rapid growth in digital signal processing applications has increased the requirement for high-speed digital systems. Multiprocessor systems are the best choice for these applications. A prior sequence of operations should be applied to the operations that described the nature of these applications before hardware implementation is produced. These operations should be scheduled and hardware allocated. This paper proposes a new scheduling technique for digital signal processing (DSP) applications has been represented by data flow graphs (DFGs). In addition, hardware allocation is implemented in the form of embedded system. A proposed scheduling technique also achieves the optimal scheduling of a DFG at design time. The optimality criteria considered in this algorithm are the maximum throughput within the available hardware resources. The maximum throughput is achieved by arranging the DFG nodes according to their inter-related data dependencies. Then, two nodes can be clustered into one compound task to reduce the overall execution time by minimizing the number of tasks to be executed that minimizing the number of cycles to execute them. Then each task is presented in form of instruction to be executed in the hardware system. A hardware system is composed of one or multiple homogenous pipelined processing elements and it is designed to meet the maximum-rate schedule.  Two implementations are proposed of the system architecture according to the number of the processing elements, namely:  the serial system and the parallel system. The serial system comprises one processing element where all tasks are processed sequentially, whilst the parallel system has four processing elements to execute tasks concurrently. These systems consist mainly of seven units: central shared memory, state table, multiway function unit buffer, execution array, processing element/s, instruction buffer and the address generation unit. The hardware components were built on an FPGA chip using Verilog HDL. In synthesis results, the parallel system has better system performance by 25.5% than the serial system. While the serial system requires smaller area size, which described by the number of slice registers and the number of the slice lookup tables (LUTs) than the parallel one. The relationship between the number of instructions that are executed in both systems, and the system area and the system performance that presented by system frequency, are studied. By increasing memories size in both systems, the system performance isn’t affected as in a serial system, and it is slightly decreased as the parallel system by 1.5% to 4.5%. In terms of the systems area, both serial system area and parallel system area are increased and in some cases are doubled. The proposed scheduling technique is shown to outperform the retaining technique, which we have chosen to compare with.  The serial system has better performance by 19.3% higher system frequency than a retiming technique. And the parallel system also outperforms the retaining technique by 51.2% higher system frequency in synthesis results.

Author Biographies

Hala AL-Zu'bi, Jordan University of Science and Technology

Hala AL-Zu'bi received her B.SC. in Computer Engineering from Yarmouk University in 2012, and M.Sc. in Computer Engineering from Jordan University of Science & Technology in 2018. Her research interests include computer architecture, hardware description language, task scheduling and data flow computing.

Osama Al-Khaleel, Jordan University of Science and Technology

Osama Al-Khaleel is an associate professor of Computer Engineering in the Department of Computer Engineering of Jordan University of Science and Technology (Irbid, Jordan), received his B.S in Electrical Engineering from Jordan University of Science and Technology in 1999, M.Sc. and Ph.D. in Computer Engineering from Case Western Reserve University, Cleveland, OH, USA in 2003 and 2006 respectively. Currently, his main research interests are in embedded systems design, reconfigurable computing, computer arithmetic, and logic design.

Ali Shatnawi, Jordan University of Science and Technology

Ali Shatnawi is a professor of computer engineering. He received the B.Sc and M.Sc in electrical and computer engineering from the Jordan University of Science and Technology (JUST) in 1989 and 1992, respectively; and the Ph.D degree in electrical and computer engineering from Concordia University, Canada, in 1996. He has been on the faculty of the Jordan University of Science and Technology since 1996. He served as the director of computer centre 1996-1999, Vice-dean 2001-2002, Dean of IT at Hashemite University 2002-2005 and dean of Computer and Information Technology, JUST, 2016-2018. His present research includes algorithms and optimizations, hardware scheduling, computer architecture and high level synthesis of DSP applications.

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Published

2021-04-10 — Updated on 2022-04-16

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How to Cite

AL-Zu’bi, H., Al-Khaleel, O., & Shatnawi, A. (2022). FPGA Implementation of Data Flow Graphs for Digital Signal Processing Applications. International Journal of Communication Networks and Information Security (IJCNIS), 13(1). https://doi.org/10.17762/ijcnis.v13i1.4928 (Original work published April 10, 2021)

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Research Articles